Gate interface engineering with doped layer

ABSTRACT

Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of, and priority to U.S. Provisional Application Ser. No. 63/040,107, filed Jun. 17, 2020, which is hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to treatments to enhance gate structures.

BACKGROUND

Logic gate performance is related to the characteristics of the materials used as well as the thickness and area of the structural layers. However, as some gate characteristics are adjusted to accommodate device scaling, challenges arise. For example, with a silicon oxide gate dielectric, capacitance may improve as thickness is reduced, which may lead to higher channel mobility and faster device performance. However, as the thickness continues to reduce, gate leakage may impact the device, and may cause reductions in device yield. Additionally, oxides with reduced thickness may be lower quality and cause shorting. High-k materials have been adopted for the gate dielectric to reduce the effective oxide thickness while limiting impact to the gate leakage. Efforts to maximize particular high-k materials have been limited due to morphology issues related to the formation of the high-k materials.

Thus, there is a need for improved systems and methods that can be used to maximize the performance of the high-k materials and enable the production of high quality devices and structures. These and other needs are addressed by the present technology.

SUMMARY

Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

In some embodiments, the silicon layer may be formed by atomic-layer deposition or epitaxial growth. The dopant may be or include one or more of nitrogen, phosphorus, or fluorine. The silicon layer may be formed to a thickness of less than or about 5 nm. Oxidizing a portion of the silicon layer may form a sacrificial oxide, and the method may also include removing the sacrificial oxide. The removing may include an in-situ dry chemical process. The removing may be performed in a first processing chamber, and the methods may also include forming an oxygen-containing material. The methods may include transferring the semiconductor substrate from the first processing chamber to a second processing chamber. The methods may include forming a high-k dielectric material overlying the oxygen-containing material. Prior to forming the high-k dielectric material, the methods may include introducing reactive ligands on the oxygen-containing material with a nitrogen-containing precursor or an oxygen-containing precursor.

The nitrogen-containing precursor may be or include ammonia. The high-k dielectric material may be or include at least one element selected from the group including of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, or strontium. The method may be performed in one or more processing chambers without exposing the semiconductor substrate to atmosphere. The silicon layer may be formed epitaxially over the semiconductor substrate, and the semiconductor substrate may be or include silicon germanium. Oxidizing a portion of the silicon layer may form a sacrificial oxide, and forming the sacrificial oxide may include a first oxidation process. During the method, oxidizing the portion of the silicon layer in contact with the semiconductor substrate may include a second oxidation process different from the first oxidation process. Oxidizing the portion of the silicon layer in contact with the semiconductor substrate may include delivering a nitrogen-and-oxygen containing precursor to the semiconductor substrate. Oxidizing the portion of the silicon layer in contact with the semiconductor substrate may occur at a temperature of less than or about 750° C.

Some embodiments of the present technology may encompass methods of forming a semiconductor structure. The methods may include removing oxide from a surface of a substrate contained in a semiconductor processing chamber. The substrate may be or include a silicon germanium fin. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating nitrogen, fluorine, or phosphorus as a dopant. The methods may include oxidizing the silicon layer to form a sacrificial oxide. The oxidizing may diffuse a portion of the dopant through the silicon layer and into the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include delivering nitrous oxide to the substrate to form an oxygen-containing material. The methods may include pre-treating the oxygen-containing material by contacting the substrate with a nitrogen-containing precursor. The methods may include forming a high-k dielectric material overlying the pre-treated oxygen-containing material.

In some embodiments, the removing may include an in-situ dry chemical process. The removing may be performed in a first processing chamber. The method may also include transferring the substrate from the first processing chamber to a second processing chamber prior to forming the high-k dielectric material. The silicon layer may be formed by atomic-layer deposition or epitaxial growth, and the silicon layer may be formed to a thickness of less than or about 5 nm. Forming the sacrificial oxide may include delivering an oxygen-containing precursor and a hydrogen-containing precursor to the substrate to form an oxygen-containing material.

Some embodiments of the present technology may encompass methods of forming a semiconductor structure. The methods may include removing a native oxide from a surface of a substrate contained in a semiconductor processing chamber. The substrate may include silicon germanium. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate. The methods may include removing the sacrificial oxide.

Such technology may provide numerous benefits over conventional systems and techniques. For example, the processes may allow dopant incorporation into a channel region of a semiconductor structure, and may produce a high quality oxide layer for a gate oxide. Additionally, the production of the gate oxide may limit extended oxidation into underlying layers. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

FIG. 1 shows a top plan view of an exemplary processing system according to embodiments of the present technology.

FIG. 2 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology.

FIGS. 3A-3I show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology.

Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.

DETAILED DESCRIPTION

As logic gate structures scale to smaller dimensions, new material structures are being sought to provide improvements. The use of high-k dielectrics increases the dielectric constant of the gate stack over conventional gate stacks that utilize materials such as silicon oxide. However, similar to silicon oxide, as material thicknesses are reduced, gate leakage increases. For example, gate leakage increases as the effective oxide thickness decreases. Hence, the inverse relationship between gate leakage and effective oxide thickness may form a limit on the performance of the transistor and the device produced.

For FinFET structures, the gate oxide overlying the fins may perform a number of functions. For example, the gate oxide may form the conductive channel region below the gate. Defects or holes within the gate oxide, such as from a lower quality oxide, may produce shorting and damage to the structure. Additionally, the gate oxide may block germanium diffusion in PFET or P-MOS regions of the device. Conventional technologies often use wet oxidation techniques, such as chemox, to form the gate oxide, along with other oxidation methods. Conventional techniques produce lower quality oxide layers, and may not be well controlled, which may over-oxidize into the fin. This may produce less robust germanium oxide materials, which may be more likely to fail under thermal or electrical stresses. The present technology overcomes these issues by forming controlled gate oxide layers from defined silicon-containing materials. These gate oxide layers may limit over oxidation of the SiGe fin material, and may provide improved electrical and thermal performance over conventional techniques. The present technology also provides mechanisms for incorporating dopants into channel regions and other substrate structures utilizing overlying layers.

Although the remaining disclosure will routinely identify specific deposition and treatment processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other processes as may occur in the described chambers. Accordingly, the technology should not be considered to be so limited as for use with the described treatment and deposition processes alone. The disclosure will discuss one possible system that can be used with the present technology to perform certain elements of the deposition or treatment operations before describing operations of an exemplary process sequence according to the present technology. It is to be understood that the technology is not limited to the equipment described, and processes discussed may be performed in any number of processing chambers and systems.

FIG. 1 shows a top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and/or curing chambers according to embodiments. The tool or processing system 100 depicted in FIG. 1 may contain a plurality of process chambers, 114A-D, a transfer chamber 110, a service chamber 116, an integrated metrology chamber 117, and a pair of load lock chambers 106A-B. The process chambers may include any number of structures or components, as well as any number or combination of processing chambers. It is to be understood that system 100 is not intended to limit tools for which chambers may be incorporated for performing processes described below. Any tool, including any number of chambers, may also be used according to some embodiments of the present technology.

To transport substrates among the chambers, the transfer chamber 110 may contain a robotic transport mechanism 113. The transport mechanism 113 may have a pair of substrate transport blades 113A attached to the distal ends of extendible arms 113B, respectively. The blades 113A may be used for carrying individual substrates to and from the process chambers. In operation, one of the substrate transport blades such as blade 113A of the transport mechanism 113 may retrieve a substrate W from one of the load lock chambers such as chambers 106A-B and carry substrate W to a first stage of processing, for example, a treatment process as described below in chambers 114A-D. The chambers may be included to perform individual or combined operations of the described technology. For example, while one or more chambers may be configured to perform a deposition or formation operation, one or more other chambers may be configured to perform a pre-treatment operation and/or one or more of the post-treatment operations described. Any number of configurations are encompassed by the present technology, which may also perform any number of additional fabrication operations typically performed in semiconductor processing.

If the chamber is occupied, the robot may wait until the processing is complete and then remove the processed substrate from the chamber with one blade 113A and may insert a new substrate with a second blade (not shown). Once the substrate is processed, it may then be moved to a second stage of processing. For each move, the transport mechanism 113 generally may have one blade carrying a substrate and one blade empty to execute a substrate exchange. The transport mechanism 113 may wait at each chamber until an exchange can be accomplished.

Once processing is complete within the process chambers, the transport mechanism 113 may move the substrate W from the last process chamber and transport the substrate W to a cassette within the load lock chambers 106A-B. From the load lock chambers 106A-B, the substrate may move into a factory interface 104. The factory interface 104 generally may operate to transfer substrates between pod loaders 105A-D in an atmospheric pressure clean environment and the load lock chambers 106A-B. The clean environment in factory interface 104 may be generally provided through air filtration processes, such as HEPA filtration, for example. Factory interface 104 may also include a substrate orienter/aligner (not shown) that may be used to properly align the substrates prior to processing. At least one substrate robot, such as robots 108A-B, may be positioned in factory interface 104 to transport substrates between various positions/locations within factory interface 104 and to other locations in communication therewith. Robots 108A-B may be configured to travel along a track system within factory interface 104 from a first end to a second end of the factory interface 104.

The processing system 100 may further include an integrated metrology chamber 117 to provide control signals, which may provide adaptive control over any of the processes being performed in the processing chambers. The integrated metrology chamber 117 may include any of a variety of metrological devices to measure various film properties, such as thickness, roughness, composition, and the metrology devices may further be capable of characterizing grating parameters such as critical dimensions, sidewall angle, and feature height under vacuum in an automated manner.

Each of processing chambers 114A-D may be configured to perform one or more process steps in the fabrication of a semiconductor structure, and any number of processing chambers and combinations of processing chambers may be used on multi-chamber processing system 100. For example, any of the processing chambers may be configured to perform a number of substrate processing operations including any number of deposition processes including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, as well as other operations including etch, pre-clean, pre-treatment, post-treatment, anneal, plasma processing, degas, orientation, and other substrate processes. Some specific processes that may be performed in any of the chambers or in any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma processing. Any other processes may similarly be performed in specific chambers incorporated into multi-chamber processing system 100, including any process described below, as would be readily appreciated by the skilled artisan.

FIG. 2 illustrates a method 200 of forming a semiconductor structure, operations of which may be performed, for example, in one or more chambers incorporated on multi-chamber processing system 100 as previously described, or any other multi-chamber system. Method 200 may include one or more operations prior to the initiation of the stated method operations, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations as denoted in the figure, which may or may not specifically be associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation process, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 200 describes the operations shown schematically in FIGS. 3A-3I, the illustrations of which will be described in conjunction with the operations of method 200. It is to be understood that FIG. 3 illustrates only partial schematic views, and a substrate may contain any number of transistor sections and additional materials having aspects as illustrated in the figures.

Method 200 may involve optional operations to develop the semiconductor structure to a particular fabrication operation. Although in some embodiments method 200 may be performed on a base structure, in some embodiments the method may be performed subsequent other material formation. As illustrated in FIG. 3A, the semiconductor structure may represent a device 300 after certain processing has been completed. For example, substrate 305 may be a planar material, or may be a structured device, which may include one or more materials configured as or defining posts, trenches, or other structures as would be understood are similarly encompassed by the present technology. Substrate 305 may include any number of materials including silicon, silicon germanium, or silicon-containing materials such as oxides, nitrides, and carbides of silicon, as well as any other materials that may be incorporated within a structure. In some embodiments encompassed by the present technology, the substrate 305 may be a portion of a silicon germanium fin, such as which may be associated with a FinFET structure, and may be part of the P-MOS region. Prior to method 200, a layer of silicon germanium may be formed on a silicon substrate, or other substrate, and may be patterned to form a fin structure. An isolation dielectric may be formed about the fins, and a trim operation may be performed to thin upper portions of the fin. It is to be understood that the figure is not to any particular scale.

Subsequent this processing or as a result of transfer of the substrate, substrate 305 may include a native oxide 310 or residual particulate material on the surface of the silicon germanium as illustrated in FIG. 3A. The exposed material at a surface of substrate 305 may be etched, planarized, or otherwise processed to produce an intermittent pattern in some embodiments. Although illustrated as a single instance, it is to be understood that device 300 may include a small section of a larger process integration that may include any number of additional sections that may be similar or different to the objects shown. For example, an N-MOS region may be positioned adjacent the structure illustrated, and may include any amount of patterning or operations performed along with or separate from the method described. Substrate 305 may be housed or positioned in a processing region of a semiconductor processing chamber, and method 200 may be performed to produce a semiconductor material on the substrate, such as a high-k dielectric material.

Method 200 may include removing a native oxide 310 from the substrate 305 in optional operation 205. Removing a native oxide 310 may be performed by any number of processes. For example, a reduction may occur by utilizing a hydrogen-containing precursor, which may reduce the oxide to ensure a relatively clean surface of the silicon germanium. Additionally, the process may include a plasma process or treatment, which may include a fluorine-containing precursor and a hydrogen-containing precursor. Fluorine-containing precursors may be or include nitrogen trifluoride as well as any other fluorine-containing precursor. Hydrogen-containing precursors may be characterized by an amine group [—NH2], or other nitrogen-containing or hydrogen-containing group. For example, hydrogen-containing precursors may be or include nitrogen-and-hydrogen-containing precursors, such as ammonia as one non-limiting example. The plasma may be generated locally or in a remote plasma region that may be fluidly coupled with the substrate processing region. A flow rate of the fluorine-containing precursor and a flow rate of the hydrogen-containing precursor may be controlled to maintain a hydrogen-to-fluorine atomic flow ratio of less than 1:2. The oxide 310 or residual material may be removed by the plasma effluents 315 as illustrated in FIG. 3B, a process which may also include a heat treatment to remove byproducts from the etch process.

Removing the native oxide in operation 205 may by an in-situ dry chemical process where the substrate surface may not be exposed to atmosphere or an oxygen-containing environment. Removing a native oxide in operation 205 may be performed in a first processing chamber in some embodiments of method 200. Method 200 may include transferring the substrate from the first processing chamber to a second processing chamber prior to forming a high-k dielectric material as will be explained below. Method 200 may include performing operations in one or more processing chambers without exposing the substrate surface to atmosphere or air, such as by maintaining a vacuum within system 100 while transferring a substrate between one or more chambers for operations of method 200. Maintaining an integrated vacuum may advantageously reduce surface contamination, as well as unwanted oxide formation. The transferring may occur between one or more chambers on a single platform, or may occur between chambers on multiple platforms. However, by utilizing a single platform, the avoidance of substrate exposure to an oxygen environment may be better secured.

A silicon-containing material may be formed or deposited on the pre-treated or cleaned substrate surface in operation 210. For example, a layer of silicon, or a silicon-containing material such as doped silicon, alloyed silicon, or a silicon-and-metalloid or silicon-and-metal material, may be formed or deposited by any number of methods to form a layer 320 overlying a surface of the substrate 305, as illustrated in FIG. 3C. In some non-limiting embodiments, silicon may be epitaxially grown conformally over a surface of the silicon germanium fin. Additionally, an atomic-layer deposition process may be performed to produce a silicon layer that is conformally deposited or formed on the substrate. The conformal formation may allow control over thickness over conventional deposition techniques. The layer may be formed to any height, and may produce a relatively high quality silicon. For example, the silicon layer 320 may be formed to several angstrom or several nanometers in height in various embodiments. In some embodiments, the layer may be formed to a thickness of less than or about 10.0 nm, and may be formed to a thickness of less than or about 8.0 nm, less than or about 5.0 nm, less than or about 4.0 nm, less than or about 3.0 nm, less than or about 2.0 nm, less than or about 1.0 nm, less than or about 9 Å, less than or about 8 Å, or less.

In some embodiments the silicon layer may be formed as amorphous silicon, and may include a dopant material during the formation process. As illustrated in FIG. 3C, dopant particles 321 may be incorporated within the silicon layer during deposition. The dopant may be delivered as an additional precursor, which may further interact with one or more silicon-containing precursors or other deposition precursors or carrier gases to incorporate dopant particles within the silicon material being formed. Exemplary dopant materials may be nitrogen, phosphorous, fluorine, or any other material that can be incorporated within the silicon structure. The materials may be delivered in any number of forms, although the materials may be delivered in more readily dissociable forms to limit additional material incorporation within the silicon layer. For example, exemplary precursors may include diatomic nitrogen, nitrogen trifluoride, fluorine, hydrogen fluoride, phosphine, or any other nitrogen-containing, fluorine-containing, or phosphorous-containing material.

Subsequent formation of the silicon layer, a portion of the layer may be oxidized at operation 215. The oxidation may be performed in any number of ways, and the oxidation may fully oxidize the layer, although the oxidation may not extend fully through the silicon layer. Oxidation operation 215 may produce a sacrificial oxide 322 by converting a portion of the silicon layer 320 into silicon oxide, up to the full layer of silicon. Oxidation operation 215 may oxidize a portion of silicon layer 320 while at least partially maintaining a portion of the silicon layer 320 in contact with the semiconductor substrate 305. For example, a controlled oxidation may be performed to limit an extension of the oxidation through the silicon-containing layer. Operation 215 may include a thermally-based reaction using steam, such as an in situ steam generation process whereby oxidation takes place at a lower rate as compared with conventional thermal techniques. Additionally, the oxidation may utilize hydrogen and oxygen together as a thermal oxidation process, as well as additional precursors. For example, in some embodiments an oxygen-containing precursor may be used, such as a nitrogen-and-oxygen-containing precursor. For example, nitrous oxide, or some other nitrogen-and-oxygen-containing precursor, and/or additional precursors, such as hydrogen for example, may be used to oxidize the portion of the silicon-containing material.

The nitrogen may serve as a carrier for oxygen and may not become part of the interface or substrate. The process may also occur slowly, which may produce a more controlled oxidation, and which may be controlled to maintain a particular thickness of silicon along the surface of substrate 305. Subsequent formation of a sacrificial oxide, a number of other fabrication operations may occur, including forming a dummy poly mask followed by dummy gate formation on the substrate. After processing has been performed, a gate oxide formation process may occur, as will be described further below.

The oxidation process may be used to facilitate additional operations as well. For example, by incorporating dopants into the silicon layer, the oxidation process may be used to thermally drive the dopants 321 through the silicon layer and into the underlying substrate as illustrated in FIG. 3D. For example, the temperature of the oxidation may allow the dopant materials to diffuse fully through the silicon layer and incorporate within the underlying materials. Incorporating fluorine, nitrogen, or phosphorous into the substrate, such as the underlying channel region that may reside underneath the gate to be formed, for example, may increase operational performance and reliability of the device formed. While doping may be performed during development of the underlying channel region, incorporating dopants subsequently with the oxidation operation may ensure high quality formation occurs through the channel region. Additionally, the formation may occur without incorporating excessive amounts of other constituents of the dopant materials, such as hydrogen, or other components of the dopants as delivered in precursor form.

One or more removal operations may be performed at optional operation 220 to remove the sacrificial oxide overlying the maintained silicon 320. As illustrated in FIG. 3E, the maintained silicon may be characterized by a thickness sufficient to maintain coverage over the silicon germanium substrate material. For example, in some embodiments the silicon layer 320 may be maintained at less than or about 5 nm, and may be maintained at less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, less than or about 5 Å, or less. The removal operation may include a selective etch, such as an oxide-selective etch. In some embodiments, a plasma etch process may be performed, such as with a fluorine-containing precursor and a hydrogen-containing precursor. The removal operation may include any of the operations described above, such as by utilizing a nitrogen trifluoride and ammonia plasma etch, which may also include an additional heat treatment or sublimation operation. Additional or alternative fluorine and hydrogen-containing precursors may also be used in some embodiments. By performing an oxide-selective etch process at operation 220, the underlying portion of silicon may be maintained or substantially maintained.

After the silicon cap material has been exposed, a second oxidation operation may be performed to oxidize the remaining silicon layer of material overlying the silicon germanium fin. Any of the previous oxidation operations may be performed to produce an oxygen-containing material 324 as illustrated in FIG. 3F, such as silicon oxide, at optional operation 225. In some embodiments the remaining silicon material may be fully converted to silicon oxide, and no residual silicon layer may remain. In some embodiments, the oxidation may utilize nitrous oxide and hydrogen as explained above. This may tightly control the oxidation to be substantially limited to the silicon material, while limiting or preventing over oxidation into the silicon germanium material. Such a thermal oxidation process may provide many benefits as explained above. For example, unlike a wet oxidation, for example, the present oxidation may produce a high quality oxide, which may limit germanium diffusion.

Additionally, some conventional oxidation processes, including wet and dry oxidation processes, may over oxidize into the silicon germanium, which may produce germanium oxide materials. Germanium oxide may be characterized by less stable bonding compared to silicon oxide, and consequently, subsequent operations may break the germanium oxide bonds. This may damage the oxide formed, or reduce the quality of the interface between the materials, which may limit the transistor efficiency, or damage the device. Forming a high-quality oxide may beneficially protect the structure during later operations as well. For example, conventional processes producing a less dense oxide may be further degraded with additional fabrication operations. As will be explained below, additional high-k dielectric operations may be performed as well as subsequent fabrication, which may include high temperature processes. For example, at some point in fabrication a flash anneal may be performed at up to 1000° C. For lower quality or less dense oxides, this may promote additional germanium diffusion due to a more porous oxide structure. The more dense thermal oxide processes according to some embodiments of the present technology may protect against diffusion during subsequent fabrication operations. By maintaining control of the oxidation according to embodiments of the present technology, high quality oxide materials with specific depth may be provided at any of the reduced thicknesses described above.

The oxygen-containing material formed may be high quality and highly ordered, meaning a crystallographic structure free of or substantially free of defects. This may provide an interface that may prevent additional materials from accessing closely to the channel region, thus preventing leakage. The resultant oxygen-containing material 324 may include silicon dioxide. The oxygen-containing material 324 formed may have a thickness of up to or about 5 Å, and may have a thickness of greater than or about 5 Å, greater than or about 10 Å, greater than or about 15 Å, greater than or about 20 Å, greater than or about 25 Å, greater than or about 30 Å, or greater.

Method 200 may include delivering a pre-treatment precursor to the substrate in optional operation 230. The pre-treatment precursor may be or include a nitrogen-containing precursor or an oxygen-containing precursor. The precursor may contact the substrate and may form or introduce reactive ligands on an exposed surface of the substrate, which is shown as ligands 325 in FIG. 3G. Unlike conventional technologies, the present technology may utilize a pre-treatment configured to produce an orderly growth of high-k dielectric material in subsequent operations.

The pre-treatment precursor may be or include any nitrogen-containing or oxygen-containing precursor. Oxygen-containing precursors may be characterized by a hydroxyl group [—OH], which may be incorporated on the surface of substrate oxygen-containing material 324. Nitrogen-containing precursors may be characterized by an amine group [—NH2], or other nitrogen-containing group. For example, nitrogen-containing precursors may be or include nitrogen-and-hydrogen-containing precursors, such as ammonia as one non-limiting example, or nitrogen-and-oxygen-containing precursors, or any other precursor including nitrogen.

The surface terminations in some embodiments may be or include a hydroxyl group or an amine-group-terminated surface. Method 200 may then include forming a high-k dielectric material overlying the oxygen-containing material at optional operation 235. The present technology may encompass any formation or deposition of the high-k material, although in some embodiments formation operation 235 may be or include an atomic layer deposition, which may utilize any number of atomic layer deposition chamber. The formation may be performed directly after pre-treating the substrate or oxygen-containing material surface, if performed, and may be performed in the same chamber as the pre-treatment or in an additional chamber, such as an additional chamber incorporated on the same system, such as system 100. In some embodiments, vacuum conditions may be maintained while the substrate is transferred from the pre-treatment chamber to the deposition or formation chamber, which may limit exposure of the substrate to air.

Where an atomic layer deposition process is performed to form the high-k dielectric material, a metal-containing precursor may be delivered to the substrate to react with the pre-treated surface. For example, a transition-metal-containing precursor, a poor-metal-containing precursor, or a lanthanide-metal-containing precursor may be delivered to the processing chamber to interact with the reactive ligands exposed on the substrate from the pre-treatment. An oxygen-containing precursor may then be delivered in a second operation, such as subsequent a purge of the metal-containing precursor. This may produce an oxide layer by atomic layer deposition, such as layer 330 a as illustrated in FIG. 3H. In one non-limiting example, a hafnium-containing precursor may be delivered in a first operation and an oxidant may be delivered in a second operation for producing a hafnium oxide film. Additional metal-containing precursors may include zirconium-containing precursors for producing zirconium-containing materials, as well as any other number of metal-containing precursors for producing additional metal oxide structures. For hafnium-containing precursors, and similarly for any alternative metals, the precursors may be or include halogen-containing precursors, oxygen-containing precursors, hydrogen-containing precursors, or carbon-containing precursors in any of which hafnium is incorporated.

For the oxidant, any oxygen-containing precursor may be used that may react with the metal-containing materials. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, nitrogen-and-oxygen-containing precursors, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material including oxygen that may be incorporated with the metal, such as hafnium, to produce a metal oxide material layer overlying the substrate. Again, any of the metal-containing materials noted above may be used in embodiments of the present technology, and may include any of the grouped metals, which may include, and may not be limited to, hafnium, zirconium, silicon, lanthanum, aluminum, titanium, strontium, or combinations of these materials, such as, for example, hafnium silicate.

When pre-treatments according to embodiments of the present technology are performed, the structure of the metal-containing material can be formed or deposited in an ordered way to produce a more uniform grain structure. This may be produced by forming the reactive ligands of the pre-treatment precursor over a more structured surface material, such as higher quality silicon or silicon oxide as produced by embodiments of the present technology. Additionally, by performing the pre-treatment exposure at certain conditions, additional improvements may be afforded.

The pre-treatment may be performed at a temperature configured to activate the precursor and/or the surface of the substrate. For example, in a situation in which a nitrogen-and-hydrogen-containing precursor may be used as the pre-treatment precursor, the substrate may be maintained at a temperature greater than or about 300° C. while delivering the precursor. Similarly, a pre-treatment with an oxygen-containing precursor may also be performed while maintaining a substrate temperature greater than or about 300° C. For any pre-treatment operation the substrate may also be maintained at a temperature greater than or about 400° C., greater than or about 500° C., greater than or about 600° C., greater than or about 700° C., greater than or about 800° C., or greater. As temperature for the pre-treatment decreases below or about 500° C., the effectiveness may be reduced. Similarly, as temperatures are increased above or about 700° C., nucleation may not be improved, and excess precursor may be incorporated on the surface, which may degrade the mobility of the device. Consequently, in some embodiments the temperature may be maintained between about 500° C. and about 700° C. during the pre-treatment.

Similar temperature ranges may affect operation of one or both of the oxidation operations, which may carefully control both the amount of maintained silicon cap material in the first oxidation, and may limit over oxidation in the second oxidation. To control a slow ingression of oxygen into the silicon material, a temperature may be maintained less than or about 900° C., and may be maintained less than or about 850° C., less than or about 800° C., less than or about 750° C., less than or about 700° C., less than or about 650° C., less than or about 600° C., or less.

Similarly, exposure time may affect the amount of nitrogen-containing precursor incorporation, and thus to limit mobility losses of the produced device, the precursor exposure may be less than or about 3 minutes, and in some embodiments the exposure time may be less than or about 2.5 minutes, less than or about 2 minutes, less than or about 1.5 minutes, less than or about 1 minute, less than or about 45 seconds, less than or about 30 seconds, less than or about 15 seconds, or less. Once an appropriate amount of amine groups have been incorporated, the formation may be performed. The formation, including atomic layer formation may be performed at any temperature, although in some embodiments atomic layer deposition may be performed at a temperature below or about the temperature at which the pre-treatment is performed, regardless of whether the operations are performed in the same or different chambers. For example, the atomic layer deposition may be performed at a second temperature relative to the pre-treatment temperature, and the formation temperature may be less than or about 500° C. in embodiments, and may be less than or about 450° C., less than or about 400° C., less than or about 350° C., less than or about 300° C., less than or about 250° C., or less.

After the layer of high-k material has been formed or deposited, one or more post-treatments may be performed. In some embodiments, the substrate may be transferred from the deposition chamber to another chamber or set of chambers for post-treating the materials at optional operation 240. Similar to that explained above, the transfer may occur on a single processing system having multiple chambers, and thus the transfer from or between any of these chambers may be performed while maintaining vacuum conditions. Method 200 may then include one or more additional post-treatment operations as noted by optional operation 245. The post-treatment operations may include one or more operations performed in one or more chambers, including multiple chambers on the same cluster tool. Post-treatment operations may include an oxidation, a nitridation, and/or a thermal anneal.

As noted above, the pre-treatment operation may be performed to provide sufficient terminal moieties to afford the uniform growth described previously, while limiting excess precursor from being incorporated with the substrate. For example, an incorporated nitrogen interface may reduce mobility of the produced transistor, or how quickly a carrier can move through the structure. Although the pre-treatment described above may further improve scaling of high-k films, if not controlled, the pre-treatment may actually degrade device mobility. However, in some embodiments, one post-treatment may include oxidizing the formed high-k material with a second oxygen-containing precursor relative to a first oxygen-containing precursor that may be used in the pre-treatment operation.

For example, an oxidation operation utilizing any of the above-noted oxygen-containing precursors may be performed to further oxidize the film after formation. The deposition or formation of the high-k film may produce a porous film, or a film including vacancies in the structure. By performing an oxidation operation, oxygen species may permeate the film filling vacancies as illustrated by layer 330 b, as well as producing an oxide material at the interface of the high-k material, such as optional layer 320 if not formed in previous operations described above. This may improve the underlying interface from the amine terminal groups, which may increase the mobility performance of the device. To limit an excessive increase in an underlying oxide layer thickness, the oxidation operation may be performed for a limited time period, and may be performed within any of the previously noted time ranges.

Post-treatment operations may additionally include further contacting the substrate with a second nitrogen-containing precursor relative to the pre-treatment nitrogen-containing precursor, when used. The second nitrogen-containing precursor may include any nitrogen-containing precursor described above, and may include nitrogen gas, as well as any nitrogen-containing precursor noted elsewhere. The second nitrogen-containing precursor may include a plasma-activated or enhanced nitrogen-containing precursor, a thermally-activated nitrogen, or some other nitrogen precursor, which may allow nitrogen radicals or nitrogen atoms to be incorporated within the high-k structure, which may stabilize the film or settle the film towards an equilibrium state. Unlike an oxidation operation, the nitridation may not increase a thickness of an underlying layer, such as silicon oxide, and may also slightly increase the k-value of the produced film.

Nitrogen incorporation may be controlled to limit the incorporation in the film, in order to maintain the structural and electrical properties. In some embodiments, a post-treatment nitridation may incorporate less than or about 20 atomic % nitrogen at a surface region of the high-k film, and may incorporate less than or about 15 atomic % nitrogen, less than or about 10 atomic % nitrogen, less than or about 8 atomic % nitrogen, less than or about 6 atomic % nitrogen, less than or about 4 atomic % nitrogen, less than or about 2 atomic % nitrogen, or less. In some embodiments, an incorporation between about 3 atomic % and about 7 atomic % may maintain a higher k-value than higher nitrogen incorporation, and may better stabilize the film than lower nitrogen incorporation. By surface region may be meant an exposed surface of the material, although the nitrogen incorporation may extend to any distance within the film, and may be consistent, or form a reducing gradient through the material.

A post-treatment oxidation or nitridation may be performed at any of the temperatures noted previously, although in some embodiments the post-treatment oxidation and/or nitridation may be performed at a temperature range below or about 500° C., and may be performed at a temperature range below or about 400° C., below or about 300° C., below or about 200° C., below or about 100° C., or less depending on the operation being performed.

A post-treatment anneal may be performed subsequent any of the operations, including any of the noted post-treatment operations. The post-treatment anneal may be performed in any chamber in which a previous operation is performed, or may involve transfer to a different chamber, such as one configured to perform a rapid thermal anneal process, for example. Again, the chamber may be incorporated on the same platform as other chambers, which may allow a transfer between chambers while maintaining vacuum conditions. The post-treatment anneal may further align the film bonding and further stabilize the film. In embodiments the post-treatment anneal may be performed at a temperature that may be above deposition or oxidation temperatures in some embodiments. For example, the post-treatment anneal may be performed at a temperature above or about 400° C., and in embodiments may be performed at a temperature above or about 500° C., above or about 600° C., above or about 700° C., above or about 800° C., above or about 900° C., or higher.

By performing a pre-treatment, oxidations, and/or post-treatments according to embodiments of the present technology, improved high-k materials and semiconductor structures may be produced. The layer of high-k material may be produced to any thickness including up to or about several nanometers. However, due to the preferred grain structure produced by the present technology, thinner effective oxide thickness may be produced without loss to gate leakage performance. High-k materials produced according to the present technology may be characterized by k-values greater than or about 10, and may be characterized by k-values greater than or about 15, greater than or about 20, greater than or about 21, greater than or about 22, greater than or about 23, greater than or about 24, greater than or about 25, or greater.

The present technology further allows improved dielectric constants compared to conventional technologies. Additionally, because of the produced grain structure, gate leakage currents associated with the film may be less than or about one tenth of the gate leakage current of a similar thickness film of silicon oxide, and the gate leakage currents may be less than or about one hundredth of the gate leakage current of a similar thickness film of silicon oxide, less than or about one thousandth of a similar thickness film of silicon oxide, less than or about 1/5,000 of a similar thickness film of silicon oxide, less than or about 1/10,000 of a similar thickness film of silicon oxide, less than or about 1/20,000 of a similar thickness film of silicon oxide, less than or about 1/50,000 of a similar thickness film of silicon oxide, less than or about 1/100,000 of a similar thickness film of silicon oxide, or less. By producing films according to embodiments of the present technology, formed films having a beneficial morphology may be produced, which may enhance the electrical characteristics of the film compared to conventional technologies.

In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology.

Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a layer” includes a plurality of such layers, and reference to “the precursor” includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups. 

The invention claimed is:
 1. A method of forming a semiconductor structure, the method comprising: forming a silicon layer over a semiconductor substrate, wherein the forming comprises: forming a silicon layer incorporating a dopant; and oxidizing a portion of the silicon layer, wherein the oxidizing drives a portion of the dopant through the silicon layer and into the semiconductor substrate.
 2. The method of forming a semiconductor structure of claim 1, wherein the silicon layer is formed by atomic-layer deposition or epitaxial growth.
 3. The method of forming a semiconductor structure of claim 1, wherein the dopant comprises one or more of nitrogen, phosphorus, or fluorine.
 4. The method of forming a semiconductor structure of claim 1, wherein the silicon layer is formed to a thickness of less than or about 5 nm.
 5. The method of forming a semiconductor structure of claim 1, wherein oxidizing a portion of the silicon layer forms a sacrificial oxide, the method further comprising: removing the sacrificial oxide, wherein the removing includes an in-situ dry chemical process.
 6. The method of forming a semiconductor structure of claim 5, wherein the removing is performed in a first processing chamber, and wherein the method further comprises forming an oxygen-containing material; transferring the semiconductor substrate from the first processing chamber to a second processing chamber; and forming a high-k dielectric material overlying the oxygen-containing material.
 7. The method of forming a semiconductor structure of claim 6, further comprising, prior to forming the high-k dielectric material, introducing reactive ligands on the oxygen-containing material with a nitrogen-containing precursor or an oxygen-containing precursor.
 8. The method of forming a semiconductor structure of claim 7, wherein the nitrogen-containing precursor comprises ammonia.
 9. The method of forming a semiconductor structure of claim 6, wherein the high-k dielectric material comprises at least one element selected from the group consisting of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, and strontium.
 10. The method of forming a semiconductor structure of claim 1, wherein the method is performed in one or more processing chambers without exposing the semiconductor substrate to atmosphere.
 11. The method of forming a semiconductor structure of claim 1, wherein the silicon layer is formed epitaxially over the semiconductor substrate, and wherein the semiconductor substrate comprises silicon germanium.
 12. The method of forming a semiconductor structure of claim 1, wherein oxidizing a portion of the silicon layer forms a sacrificial oxide, wherein forming the sacrificial oxide comprises a first oxidation process, and wherein the method further comprises: oxidizing the portion of the silicon layer in contact with the semiconductor substrate comprises a second oxidation process different from the first oxidation process.
 13. The method of forming a semiconductor structure of claim 1, wherein the oxidizing the portion of the silicon layer in contact with the semiconductor substrate comprises delivering a nitrogen-and-oxygen containing precursor to the semiconductor substrate.
 14. The method of forming a semiconductor structure of claim 13, wherein the oxidizing the portion of the silicon layer in contact with the semiconductor substrate occurs at a temperature of less than or about 750° C.
 15. A method of forming a semiconductor structure, the method comprising: removing oxide from a surface of a substrate contained in a semiconductor processing chamber, wherein the substrate comprises a silicon germanium fin; forming a silicon layer over a semiconductor substrate, wherein the forming comprises: forming a silicon layer incorporating nitrogen, fluorine, or phosphorus as a dopant; and oxidizing the silicon layer to form a sacrificial oxide, wherein the oxidizing diffuses a portion of the dopant through the silicon layer and into the semiconductor substrate; removing the sacrificial oxide; delivering nitrous oxide to the substrate to form an oxygen-containing material; pre-treating the oxygen-containing material by contacting the substrate with a nitrogen-containing precursor; and forming a high-k dielectric material overlying the pre-treated oxygen-containing material.
 16. The method of forming a semiconductor structure of claim 15, wherein the removing includes an in-situ dry chemical process.
 17. The method of forming a semiconductor structure of claim 16, wherein the removing is performed in a first processing chamber, and wherein the method further comprises transferring the substrate from the first processing chamber to a second processing chamber prior to forming the high-k dielectric material.
 18. The method of forming a semiconductor structure of claim 15, wherein the silicon layer is formed by atomic-layer deposition or epitaxial growth, and wherein the silicon layer is formed to a thickness of less than or about 5 nm.
 19. The method of forming a semiconductor structure of claim 15, wherein forming the sacrificial oxide comprises delivering an oxygen-containing precursor and a hydrogen-containing precursor to the substrate to form an oxygen-containing material.
 20. A method of forming a semiconductor structure, the method comprising: removing a native oxide from a surface of a substrate contained in a semiconductor processing chamber, wherein the substrate comprises silicon germanium; forming a silicon layer over a semiconductor substrate, wherein the forming comprises: forming a silicon layer incorporating a dopant; and oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate, wherein the oxidizing drives a portion of the dopant through the silicon layer and into the semiconductor substrate; and removing the sacrificial oxide. 